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features ? compliant to the 40gbase-sr4 and xlppi specifcation per ieee 802.3ba-2010 and supporting 40g-ib-qdr / 20g-ib-ddr / 10g-ib-sdr applications ? compliant to the industry standard sff-8436 qsfp+ specifcation revision 3.5 ? power level 1: max power <1.5w ? high port density: 21mm horizontal port pitch ? push-pull tab: ease of transceiver insertion and extraction; tab front clip color coded "black" for sr4 identifcation ? operate at 10.3125 gbps per channel with 64b/66b encoded data for 40gbe application and at 10 gbps with 8b/10b compatible encoded data for 40g-ib-qdr application ? links up to 100m using om3 fber and 150m using om4 fber ? supports optical interoperability with 10gbase- sr modules per ieee 802.3ae standard provided the receiver overload of 10g modules sustains up to 2.4 dbm input optical power ? 0 to 70c case temperature operating range ? proven high reliability 850 nm technology: avago vcsel array transmitter and avago pin array receiver ? hot pluggable transceiver for servicing and ease of installation ? two wire serial (tws) interface with maskable interrupts for expanded functionality ? utilizes a standard 12/8 lane optical fber with mtp ? (mpo) optical connector for high density and thin, light-weight cable management applications ? 40gbe and 40g-ib-qdr / 20g-ib-ddr / 10g-ib-sdr interconnects ? datacom/telecom switch & router connections ? data aggregation and backplane applications ? proprietary protocol and density applications description the avago technologies afbr-79eqpz is a four-channel, pluggable, parallel, fiber-optic qsfp+ transceiver with an integrated push-pull tab for 40 gigabit ethernet (40gbe) application. this transceiver is a high performance module for short-range multi-lane data communication and inter - connect applications. it integrates four data lanes in each direction with 40 gbps aggregate bandwidth. each lane can operate at 10.3125 gbps up to 100 m using om3 fber or 150 m using om4 fber. these modules support 4 x 10g infniband (ib) quadruple data rate (40g-ib-qdr) applica - tions and are backwards compatible to the 4 x 5g ib dual data rate (20g-ib-ddr) and 4 x 2.5g ib single data rate (10g-ib-sdr) applications as well. the push-pull tab facili - tates the insertion and extraction of these transceivers in such high density environment. these modules are designed to operate over multimode fber systems using a nominal wavelength of 850nm. the electrical interface uses a 38 contact edge type connec - tor. the optical interface uses an 8 or 12 fber mtp ? (mpo) connector. this module incorporates avago technolo - gies proven integrated circuit and vcsel technology to provide reliable long life, high performance, and consis - tent service. the integrated push-pull tab facilitates the insertion and extraction of these modules in all applica - tions. part number ordering options afbr-79eqpz 40gbe and 40g-ib-qdr/20g-ib-ddr/10g- ib-sdr with full real-time digital diagnos - tic monitoring and push-pull tab AFBR-79Q4EKZ* evaluation board afbr-79q2ekz** evaluation kit * includes gui and user guide ** includes gui, user guide, i-port and power supply afbr-79eqpz qsfp+ pluggable, parallel fiber-optics module for 40 gb ethernet and infniband applications data sheet patent - www.avagotech.com/patents
2 transmitter the optical transmitter portion of the transceiver (see figure 1) incorporates a 4-channel vcsel (vertical cavity surface emitting laser) array, a 4-channel input bufer and laser driver, diagnostic monitors, control and bias blocks. the transmitter is designed for en 60825 and cdrh eye safety compliance; class 1m out of the module. the tx input bufer provides cml compatible diferential inputs presenting a nominal diferential input impedance of 100 ohms. ac coupling capacitors are located inside the qsfp+ module and are not required on the host board. for module control and interrogation, the control interface (lvttl compatible) incorporates a two wire serial (tws) interface of clock and data signals. diagnostic monitors for vcsel bias, module temperature, and module power supply voltage are implemented and results are available through the tws interface. alarm and warning thresholds are established for the monitored attributes. flags are set and interrupts gener - ated when the attributes are outside the thresholds. flags are also set and interrupts generated for loss of input signal (los) and transmitter fault conditions. all fags are latched and will remain set even if the condition initiating the latch clears and operation resumes. all interrupts can be masked and fags are reset by reading the appropriate fag register. the optical output will squelch for loss of input signal unless squelch is disabled. fault detection or channel deactivation through the tws interface will disable the channel. status, alarm/warning and fault in - formation are available via the tws interface. to reduce the need for polling, the hardware interrupt signal is pro - vided to inform hosts of an assertion of alarm, warning, los and/or tx fault. receiver the optical receiver portion of the transceiver (see figure 1) incorporates a 4-channel pin photodiode array, a 4-channel tia array, a 4 channel output bufer, diagnostic monitors, and control and bias blocks. the rx output bufer provides cml compatible diferential outputs for the high speed electrical interface presenting nominal sin - gle-ended output impedances of 50 ohms to ac ground and 100 ohms diferentially that should be diferentially terminated with 100 ohms. ac coupling capacitors are located inside the qsfp+ module and are not required on the host board. diagnostic monitors for optical input power are implemen-ted and results are available through the tws interface. alarm and warning thresholds are established for the mon - itored attributes. flags are set and interrupts gene-rated when the attributes are outside the thresholds. flags are also set and interrupts generated for loss of optical input signal (los). all fags are latched and will remain set even if the condition initiating the fag clears and operation resumes. all interrupts can be masked and fags are reset upon reading the appropriate fag register. the electrical output will squelch for loss of input signal (unless squelch is disabled) and channel de-activation through tws inter - face. status and alarm/warning information are available via the tws interface. to reduce the need for polling, the hardware interrupt signal is provided to inform hosts of an assertion of alarm, warning and/or los. warning class 1m laser product: invisible laser radiation, do not view directly with optical instruments caution! viewing the laser output with certain optical instruments (for example, eye loupes, magnifers and microscopes) within a distance of 100 mm may pose an eye hazard. caution! use of controls or adjustments or performance of procedures other than those specifed herein may result in hazardous radiation exposure. note: standard used for classifcation: en 60825-1:2007 invisible laser radiation do not view directly with optical instruments class 1m laser product
3 figure 2. application reference diagram asic (serdes) rx 1 rx 2 rx 3 rx 4 tx 4 tx 3 tx 2 tx 1 module card edge (host interface) optical connector/port (optical interface) tx in p tx in n rx out p rx out n host board (only one channel shown for simplicity) qsfp + module rx tx host edge card connector control signal interface the module has the following low speed signals for control and status: modsell, lpmode, resetl, modprsl, intl. in addition, there is an industry standard two wire serial interface scaled for 3.3 volt lvttl. it is implemented as a slave device. signals and timing characteristics are further defned in the control interface section. the reg - isters of the serial interface memory are defned in the memory map section and corresponding avago technol - ogies qsfp+ memory map document. high speed electrical signal interface figure 2 shows the interface between an asic/serdes and the qsfp+ module. for simplicity, only one channel is shown. the high speed signal lines are ac-coupled 100 ohm diferential lines. the ac coupling is inside the qsfp+ module and not required on the host board. the 100 ohm diferential terminations are inside the qsfp+ module for the transmitter lines and at the host asic/serdes for the receiver lines. all transmitter and receiver electrical chan - nels are compliant to module xlppi specifcations per ieee 802.3ba. figure 1. transceiver block diagram din[4:1][p/n] (8) tx input buer 4 channels laser driver 4 channels rx output buer 4 channels tia 4 channels control diagnostic monitors 1x4 vcsel array optical interface electrical interface dout[4:1][p/n] (8) scl sda modsell lpmode modpresl resetl intl 1x4 pin array
4 regulatory & compliance various standard and regulations apply to the modules. these include eye-safety, emc, esd and rohs. see the regulatory section for details regarding these and com- ponent recognition. please note the module transmitter is a class 1m laser product C do not view radiation directly with optical instruments. see regulatory compliance table for details. package outline the module is designed to meet the package outline defned in the qsfp+ sff-8436 specifcation. see the package outline and host board footprint fgures (figures 13 C 16) for details. handling and cleaning the transceiver module can be damaged by exposure to current surges and over voltage events. care should be taken to restrict exposure to the conditions defned in the absolute maximum ratings. wave soldering, refow sol - dering and/or aqueous wash process with the modules on board are not recommended. normal handling precau - tions for electrostatic discharge sensitive devices should be observed. each module is supplied with an inserted port plug for protection of the optical ports. this plug should always be in place whenever a fber cable is not inserted. the optical connector includes recessed elements that are exposed whenever a cable or port plug is not inserted. prior to insertion of a fber optic cable, it is recommended that the cable end be cleaned to avoid contamination from the cable plug. the port plug ensures the optics remains clean and no additional cleaning should be needed. in the event of contamination, dry nitrogen or clean dry air at less than 20 psi can be used to dislodge the contamina - tion. the optical port features (e.g. guide pins) preclude use of a solid instrument. liquids are also not advised. digital diagnostic monitoring digital diagnostic monitoring is available for afbr- 79eqpz. the information provides opportunity for pre - dictive failure identifcation, compliance prediction, fault isolation and component monitoring. predictive failure identifcation C the diagnostic informa - tion allows the host system to identify potential link problems. once identifed, a failover technique can be used to isolate and replace suspect devices before system uptime is impacted. compliance prediction C the real-time diagnostic para- meters can be monitored to alert the system when op - erating limits are exceeded and compliance cannot be ensured. as an example, the real time average receiver optical power can be used to assess the compliance of the cable plant and remote transmitter. fault isolation C the diagnostic information can allow the host to pinpoint the location of a link problem and accelerate system servicing and minimize downtime. component monitoring C as part of host system qualif- cation and verifcation, real time transceiver diagnostic in - formation can be combined with system level monitoring to ensure performance and operating environment are meeting application requirements. digital diagnostic monitoring for the following attributes is implemented. transceiver module temperature C represents the module internal temperature (lower page 0 bytes 22-23) transceiver module power supply C reports the module +3.3v supply voltage (lower page 0 bytes 26-27) transmitter laser bias current C reports the dc laser bias current for each transmitter channel (lower page 0 bytes 42-43 for ch.1, bytes 44-45 for ch.2, bytes 46-47 for ch.3, bytes 48-49 for ch.4) receiver input power C reports the average input optical power for each receiver channel (lower page 0 bytes 34-35 for ch.1, bytes 36-37 for ch.2, bytes 38-39 for ch.3, bytes 40-41 for ch.4) all diagnostic monitor attributes are two-byte felds. to maintain coherency, the host must access these with single two-byte read sequences. for each monitored attribute, alarm and warning thresh - olds are established. flags are set and interrupts gener - ated when the attributes are outside the thresholds. all fags are latched and will remain set even if the condition initiating the fag clears. a mask bit that can be set to prevent assertion of interrupt for each individual attribute exists for every monitor fag. entries in the mask felds are volatile.
5 absolute maximum ratings stress in excess of any of the individual absolute maximum ratings can cause immediate catastrophic damage to the module even if all other parameters are within recommended operating conditions. it should not be assumed that lim - iting values of more than one parameter can be applied to the module concurrently. exposure to any of the absolute maximum ratings for extended periods can adversely afect reliability. parameter symbol min max units reference storage temperature ts -40 85 c 3.3 v power supply voltage vcc -0.5 3.6 v data input voltage C single ended -0.5 vcc+0.5 v data input voltage C diferential |v dip - v din | 1.0 v 1 control input voltage vi -0.5 vcc+0.5, 3.6 v control output current io -20 20 ma relative humidity rh 5 95 % note: 1. this is the maximum voltage that can be applied across the diferential inputs without damaging the input circuitry. recommended operating conditions recommended operating conditions specify parameters for which the optical and electrical characteristics hold unless otherwise noted. optical and electrical characteristics are not defned for operation outside the recommended operating conditions, reliability is not implied and damage to the module may occur for such operation over an ex - tended period of time. parameter symbol min typ max units reference case temperature tc 0 40 70 c 1 3.3 v power supply voltage vcc 3.135 3.3 3.465 v signal rate per channel 10.3125 gbd 2 control* input voltage high vih 2 vcc+.3 v control* input voltage low vil -0.3 0.8 v two wire serial (tws) interface clock rate 400 khz power supply noise 50 mvpp 3 receiver diferential data output load 100 ohms fiber length: 2000 mhz?km 50m mmf (om3) 0.5 100 m 4 fiber length: 4700 mhz?km 50m mmf (om4) 0.5 150 m * control signals, lvttl (3.3 v) compatible notes: 1. the position of case temperature measurement is shown in figure 8. 2. 64b/66b coding is assumed 3. power supply noise is defned as the peak-to-peak noise amplitude over the frequency range at the host supply side of the recommended power supply flter with the module and recommended flter in place. voltage levels including peak-to-peak noise are limited to the recommended operating range of the associated power supply. see figure 9 for recommended power supply flter. 4. channel insertion loss of 1.9db (om3) / 1.5db (om4) included with 1.5db (om3) / 1db (om4) allocated for connection and splice loss. transceiver electrical characteristics* the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c, vcc = 3.3 v parameter symbols min typ max units reference transceiver power consumption 1.5 w transceiver power supply current 475 ma transceiver power on initialization time t pwr init 2000 ms 1 * for control signal timing including modsell, lpmode, resetl, modprsl, intl, scl and sda see control interface section. note: 1. power on initialization time is the time from when the supply voltages reach and remain above the minimum recommended operating conditions to the time when the module enables tws access. the module at that point is fully functional.
6 transmitter electrical characteristics the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c, vcc = 3.3 v parameter symbol min typ max units notes los assert threshold: tx data input diferential peak-to-peak voltage swing vdi pp los 50 mvpp los hysteresis 0.5 4 db 1 parameter (from table 86a-2 of ieee 802.3ba) test point* min typ max units notes/conditions single ended input voltage tolerance [2] tp1a -0.3 4 v referred to tp1 signal common ac common mode input voltage tolerance tp1a 15 mv rms diferential input return loss tp1 see ieee 802.3ba 86a.4.1.1 db 10 mhz to 11.1 ghz diferential to common-mode input return loss tp1 10 db 10 mhz to 11.1 ghz j2 jitter tolerance tp1a 0.17 ui defned in ieee 802.3ba spec j9 jitter tolerance tp1a 0.29 ui defned in ieee 802.3ba spec data dependent pulse width shrinkage (ddpws) tolerance tp1a 0.07 ui eye mask coordinates: x1, x2 y1, y2 tp1a specification values 0.11, 0.31 95, 350 ui mv hit ratio = 5x10 -5 * see figure 6 for test point defnitions. note: 1. los hysteresis is defned as 20*log(los de-assert level / los assert level). 2. the single ended input voltage tolerance is the allowable range of the instantaneous input signals 0 -y1 y1 0 1-x1 x1 1 time (ui) di?erential amplitude (mv) y2 -y2 x2 1-x2 figure 3. electrical eye mask coordinates at hit ratio 5 x 10 -5 hits per sample
7 receiver electrical characteristics the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c, vcc = 3.3 v parameter (from table 86a-3 of ieee 802.3ba) test point* min typ max units notes/conditions single ended output voltage tp4 -0.3 4 v referred to signal common ac common mode voltage (rms) tp4 7.5 mv rms termination mismatch at 1mhz tp4 5 % diferential output return loss tp4 see ieee 802.3ba 86a.4.2.1 db 10 mhz to 11.1 ghz common-mode output return loss tp4 see ieee 802.3ba 86a.4.2.2 db 10 mhz to 11.1 ghz output transition time 20% to 80% tp4 28 ps j2 jitter output tp4 0.42 ui j9 jitter output tp4 0.65 ui eye mask coordinates: x1, x2 y1, y2 tp4 specification values 0.29, 0.5 150, 425 ui mv hit ratio = 5x10 -5 * see figure 6 for test point defnitions. dierential amplitude [mv] normalized time [ui] 0 x1 x2 1-x1 1.0 y2 -y2 y1 -y1 0 figure 4. rx electrical eye mask coordinates (tp4) at hit ratio 5 x 10 -5 hits per sample
8 transmitter optical characteristics the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c, vcc = 3.3 v parameter (from table 86-6 of ieee 802.3ba) test point* min typ max units notes/conditions center wavelength tp2 840 850 860 nm rms spectral width tp2 0.65 nm rms spectral width is the stan - dard deviation of the spectrum average launch power, each lane tp2 -7.6 2.4 dbm optical modulation amplitude (oma) each lane tp2 -5.6 3 dbm even if the tdp<0.9 db, the oma minimum must exceed -5.6 dbm diference in launch power between any two lanes (oma) tp2 4 db peak power, each lane tp2 4 dbm launch power in oma minus tdp, each lane tp2 -6.5 dbm transmitter and dispersion penalty (tdp), each lane tp2 3.5 db extinction ratio tp2 3 db optical return loss tolerance tp2 12 db encircled fux tp2 86% at 19 fm, 30% at 4.5 fm if measured into type a1a.2 50 m fber in accordance with en 61280-1-4 eye mask coordinates: x1, x2, x3, y1, y2, y3 tp2 specification values 0.23, 0.34, 0.43, 0.27, 0.35, 0.4 ui hit ratio = 5x10 -5 average launch power of off transmitter, each lane tp2 -30 dbm * see figure 6 for test point defnitions. figure 5. transmitter eye mask defnitions at hit ratio 5 x 10 -5 hits per sample normalizd amplitude [ua] 1-y2 y2 0.5 1-y1 y1 1+y3 -y3 normalized time [ui] 0 x1 x2 1-x2 1-x1 1.0 x3 1-x3 1 0 x1 = 0.23 x2 = 0.34 x3 = 0.43 y1 = 0.27 y2 = 0.35 y3 = 0.40
9 receiver optical characteristics the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c, vcc = 3.3 v parameter (from table 86-8 of ieee 802.3ba) test point* min typ max units notes/conditions center wavelength, each lane tp3 840 850 860 nm damage threshold 1 tp3 3.4 dbm maximum average power at receiver input, each lane tp3 2.4 dbm receiver refectance tp3 -12 db optical modulation amplitude (oma), each lane tp3 3 dbm stressed receiver sensitivity in oma, each lane tp3 -5.4 dbm measured with conformance test signal at tp3 for ber = 10e-12 conditions of stressed receiver sensitivity: 2 tp3 vertical eye closure penalty, each lane tp3 1.9 db stressed eye j2 jitter, each lane tp3 0.30 ui stressed eye j9 jitter, each lane tp3 0.47 ui oma of each aggressor lane tp3 -0.4 dbm peak power, each lane tp3 4 dbm los assert tp3 -30 dbm los de-assert C oma tp3 -7.5 dbm los hysteresis tp3 0.5 db * see figure 6 for test point defnitions. note: 1. the receiver shall be able to tolerate, without damage, continuous exposure to a modulated optical input signal having this power level on one lane. the receiver does not have to operate correctly at this input power 2. vertical eye closure penalty and stressed eye jitter are test conditions for measuring stressed receiver sensitivity. they are not characteristics of the receiver. the apparent discrepancy between vecp and tdp is because vecp is defned at eye center while tdp is defned with 0.15 ui ofsets of the sampling instant qsfp + rx qsfp + tx electrical connector fiber optical patch cord electrical connector tp 5 tp 4a tp 2 tp 1a tp 4 tp 0 tp 1 tp 3 asic/ serdes asic/ serdes tp0 : host asic transmitter output at asic package contact on the host board tp1 : host asic transmitter output across the host board at the input side of the host qsfp+ electrical connector tp1a : host asic transmitter output across the host board at the output side of the host qsfp+ electrical connector tp2 : qsfp+ transmitter optical output at the end of a 2 m-to-5 m patch cord tp3 : qsfp+ receiver optical input at the end of the fber tp4a : qsfp+ receiver electrical output at the input side of the host qsfp+ electrical connector tp4 : qsfp+ receiver electrical output at the output side of the host qsfp+ electrical connector tp5 : host asic receiver input at asic package contact on the host board figure 6. test point defnitions
10 regulatory compliance table feature test method performance electrostatic discharge (esd) to the electrical contacts jedec human body model (hbm) (jesd22-a114-b) jedec charge device model (cdm) (jesd22-c101d) transceiver module withstands 1 kv on high- speed pins and 2 kv on low-speed pins transceiver module withstands 250v electrostatic discharge (esd) to optical connector gr1089 10 discharges of 8 kv on the electrical faceplate with device inserted into a panel electrostatic discharge (esd) to optical connector variation of en 61000-4-2 air discharge of 15 kv(min) to connector w/o damage electromagnetic interference (emi) fcc part 15 cenelec en55022 (cispr 22a) vcci class 1 typically passes with 10 db margin. actual performance dependent on enclosure design immunity variation of en 61000-4-3 typically minimum efect from a 10 v/m feld swept from 80 mhz to 1 ghz applied to the module without a chassis enclosure laser eye safety and equipment type testing en 60825-1:2007 pout: en ael & us fda cdrh class 1m component recognition underwriters laboratories and canadian standards association joint component recognition for information technology equipment including electrical business equipment ul file number: e173874 rohs compliance bs en 1122:2001 mtd b by icp for cadmium, epa method 3051a by icp for lead and mercury, epa method 3060a & 7196a by uv/vis spectrophotometry for hexavalent chromium. epa method 3540c/3550b by gc/ms for ppb and pbde bs en method by icp and epa methods by icp, uv/vis spectrophotometry and gc/ms. less than 100 ppm of cadmium, less than 1000 ppm of lead, mercury, hexavalent chromium, polybrominated biphenyls, and polybrominated biphenyl esters.
11 qsfp+ transceiver pad layout figure 7. qsfp+ transceiver pad layout pin logic symbol description plug sequence notes 1 gnd ground 1 1 2 cml-i tx2n transmitter inverted data input 3 3 cml-i tx2p transmitter non-inverted data input 3 4 gnd ground 1 1 5 cml-i tx4n transmitter inverted data input 3 6 cml-i tx4p transmitter non-inverted data input 3 7 gnd ground 1 1 8 lvttl-i modsell module select 3 9 lvttl-i resetl module reset 3 10 vcc rx +3.3v power supply receiver 2 2 11 lvcmos-i/o scl 2-wire serial interface clock 3 12 lvcmos-i/o sda 2-wire serial interface data 3 13 gnd ground 1 1 14 cml-o rx3p receiver non-inverted data output 3 15 cml-o rx3n receiver inverted data output 3 16 gnd ground 1 1 17 cml-o rx1p receiver non-inverted data output 3 18 cml-o rx1n receiver inverted data output 3 19 gnd ground 1 1 20 gnd ground 1 1 21 cml-o rx2n receiver inverted data output 3 22 cml-o rx2p receiver non-inverted data output 3 23 gnd ground 1 1 24 cml-o rx4n receiver inverted data output 3 25 cml-o rx4p receiver non-inverted data output 3 26 gnd ground 1 1 27 lvttl-o modprsl module present 3 28 lvttl-o intl interrupt 3 29 vcc tx +3.3v power supply transmitter 2 2 30 vcc1 +3.3v power supply 2 2 31 lvttl-i lpmode low power mode 3 32 gnd ground 1 1 33 cml-i tx3p transmitter non-inverted data input 3 34 cml-i tx3n transmitter inverted data input 3 35 gnd ground 1 1 36 cml-i tx1p transmitter non-inverted data input 3 37 cml-i tx1n transmitter inverted data input 3 38 gnd ground 1 1 notes: 1. gnd is the symbol for signal supply (power) common for the qsfp+ module. all are common within the qsfp+ module and all module voltages are referenced to this potential unless otherwise noted. connect these directly to the host board signal-common ground plane 2. vcc rx, vcc1 and vcc tx are the receiver and transmitter power supplies and shall be applied concurrently. card edge top side viewed from top tx3p gnd tx1p tx1n gnd intl tx3n gnd 19 bottom side viewed from bottom vccrx modsell tx2p tx2n gnd tx4p tx4n gnd resetl modprsl 7 8 9 10 11 12 13 14 15 16 17 18 5 4 3 2 1 6 gnd rx1n rx1p gnd rx3n rx3p gnd gnd rx2n gnd rx2p rx4n rx4p gnd gnd scl vcctx sda 28 27 26 25 24 23 22 21 20 31 30 29 33 34 35 32 36 38 37 lpmode vcc1
12 figure 10. transmitter data input equivalent circuit figure 9. recommended power supply filter qsfp+ module 1 h 0.1 f 0.1 f 1 h 22 f 0.1 f 22 f vcc_host = 3.3 volt vcc tx vcc rx gnd gnd 0.1 f 1 h 22 f vcc1 gnd 22 f figure 8. case temperature measurement point dpx 50 50 vcc33 signal path (pos) vcc25 dnx vcc33 signal path (neg) vcc25 measurement point clip color coded "black" for sr4
13 figure 11. receiver data output equivalent circuit figure 12. tws interface bus timing d o u tp si g n a l pa th (po s ) si g n a l pa th (n e g) vc c 2 5 vc c 2 5 d o u tn vc c 3 3 50 ? 50 ? t su,sto scl start t hd,sda t low restart stop t high t hd,dat t f t r sda in t r t su,dat t su,sda t f t buf t buf start
14 package outline, host pcb footprint and bezel design all dimensions in mm figure 13. mechanical package outline 53 8.50 12.9 98 b b 18.35 3 131.8 1 flat surface 8.20 clip color coded "black" for sr4
15 all dimensions in mm figure 14. qsfp+ host board mechanical footprint notes: 1. datum x & y are established by the customer?s ?ducial 2. datum a is the top surface of the host board 3. location of the edge of pcb is application speci?c 4. finished hole size cross-hatched area denotes component and trace keep-out (except chassis ground) this area denotes component keep-out (traces allowed) 22.15 19.00 3.10 7.60 1.10 19 20 1 38 7.20 3.40 16.80 c k 17.90 ref. y x basic basic 3.10 7.60 l 11.30 min. 10.60 37.00 max. ?1.05 0.05 12 plc m ?0.10 a s k s l 9.00 6 plc
16 figure 15. qsfp+ host board mechanical footprint detail figure 16. host board bezel design all dimensions in mm 19 1 20 38 16.80 2.51 ?1.55 0.05 ?0.05 a x s k ?1.55 0.05 ?0.05 a x y 1 5.18 1 3 3 1.80 0.03 0.05 a c l-k 0.35 0.03 0.05 a c l-k 19.20 max. 2 15.02 max. datum axis c 22.15 notes: 1. centerline of pad 2. surface traces permitted within this length 3. indicated holes are optional 0.80 0.20 0.20 7.40 7.00 c k l all dimensions in mm 10.15 0.1 typ a 0.15 0.1 (bottom of cut-out in bezel to top of pc board) 20 0.1 typ r0.3 typ b bezel 21 0.1 1 43 0.3 2 37 max 2 notes: minimum pitch dimension for individual cages. dimension baseline is datum or . 3. not recommended for pci applications. 2 1 k l
17 control interface the control interface combines dedicated signal lines for modsell, lpmode, resetl, modprsl, intl with two-wire serial (tws), interface clock (scl) and data (sda), signals to provide users rich functionality over an efcient and easily used interface. the tws interface is implemented as a slave device and compatible with industry standard two-wire serial protocol. it is scaled for 3.3 volt lvttl. outputs are high-z in the high state to support busing of these signals. signal and timing characteristics are further defned in the control i/o characteristics section. for more details, see qsfp+ sff-8436. modsell the modsell is an input signal. when held low by the host, the module responds to 2-wire serial communica - tion commands. the modsell allows the use of multiple qsfp+ modules on a single 2-wire interface bus. when the modsell is high, the module will not respond to or acknowledge any 2-wire interface communication from the host. modsell signal input node is biased to the high state in the module. in order to avoid conficts, the host system shall not attempt 2-wire interface communica - tions within the modsell de-assert time after any qsfp+ module is deselected. similarly, the host must wait at least for the period of the modsell assert time before communi - cating with the newly selected module. the assertion and de-assertion periods of diferent modules may overlap as long as the above timing requirements are met. resetl the resetl signal is pulled to vcc in the qsfp+ module. a low level on the resetl signal for longer than the minimum pulse length (t_reset_init) initiates a complete module reset, returning all user module settings to their default state. module reset assert time (t_init) starts on the rising edge after the low level on the resetl pin is released. during the execution of a reset (t_init) the host shall disregard all status bits until the module indicates a completion of the reset interrupt. the module indicates this by posting an intl signal with the data_not_ready bit negated. note that on power up (including hot insertion) the module will post this completion of reset interrupt without requiring a reset. lpmode low power mode. when held high by host, the module is held at low power mode. when held low by host, the module operates in the normal mode. for class 1 power level modules (1.5w), low power mode has no efect. modprsl modprsl is pulled up to vcc_host on the host board and grounded in the module. the modprsl is asserted low when module is inserted into the host connector, and deasserted high when the module is physically absent from the host connector. intl intl is an output signal. when low, it indicates a pos - sible module operational fault or a status critical to the host system. the host identifes the source of the inter - rupt using the 2-wire serial interface. the intl signal is an open collector output and must be pulled to host supply voltage on the host board. a corresponding soft status intl signal is also available in the transceiver memory page 0 address 2 bit 1. soft status and control a number of soft status signals and controls are avail - able in the afbr-79eqpz transceiver memory and acces - sible through the tws interface. some soft status signals include receiver los, optional transmitter los, transmitter fault and diagnostic monitor alarms and warnings. some soft controls include transmitter disable (tx_dis), receiver output disable (rx_dis), transmitter squelch disable (tx_ sqdis), receiver squelch disable (rx_sqdis), and masking of status signal in triggering intl. all soft status signals and controls are per channel basis. all soft control entries are volatile.
18 receiver los the receiver los status signal is on page 0 address 3 bits 0-3 for channels 1-4 respectively. receiver los is based on input optical modulation amplitude (oma). this status register is latched and it is cleared on read. transmitter los the transmitter los status signal is on page 0 address 3 bits 4-7 for channels 1-4 respectively. transmitter los is based on input diferential voltage. this status register is latched and it is cleared on read. transmitter fault the transmitter fault status signal is on page 0 address 4 bits 0-3 for channels 1-4 respectively. conditions that lead to transmitter fault include laser fault, which occurs gen - erally at transceiver end of life. in addition, unbalanced electrical input data can cause transmitter fault to be trig - gered. when fault is triggered, the corresponding trans - mitter channel output will be disabled. module reset or toggling of soft transmitter disable can restore the trans - mitter channel function unless fault condition persists. this status register is latched and it is cleared on read. transmitter disable the transmitter disable control is on page 0 address 86 bits 0-3 for channels 1-4 respectively. when in transmit - ter fault, toggling the transmitter disable bit signals the transmitter channel to exit the fault state and restores the channel function, unless fault condition persists. receiver disable the receiver disable control is on page 3 address 241 bits 4-7 for channels 1-4 respectively. transmitter squelch disable the transmitter squelch disable control is on page 3 address 240 bits 0-3 for channels 1-4 respectively. afbr- 79eqpz transceivers have transmitter output squelch function enabled as default. receiver squelch disable the receiver squelch disable control is on page 3 address 240 bits 4-7 for channels 1-4 respectively. afbr-79eqpz transceivers have receiver output squelch function enabled as default.
19 i/o timing for control and status functions the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c, vcc = 3.3 v parameter symbol min typ max units reference initialization time t_init 2000 ms time from power on, hot plug or rising edge of reset until the module is fully functional. this time does not apply to non power level 0 modules in the low power state lpmode assert time ton_lpmode 100 s time from assertion of lpmode until the module power consumption enters power level 1 interrupt assert time ton_intl 200 ms time from occurrence of condition triggering intl until vout:intl=vol interrupt de-assert time tof_intl 500 s time from clear on read operation of associated fag until vout:intl=voh. this includes deassert times for rx los, tx fault and other fag bits reset init assert time t_reset_init 2 s a reset is generated by a low level longer than the minimum reset pulse time present on the resetl pin reset assert time t_reset 2000 ms time from rising edge on the resetl pin until the module is fully functional serial bus hardware ready time t_serial 2000 ms time from power on until module responds to data transmission over the 2-wire serial bus monitor data ready time t_data 2000 ms time from power on to data not ready, bit 0 of byte 2, deasserted and intl asserted rx los assert time ton_los 100 ms time from rx los state to rx los bit set and intl asserted tx fault assert time ton_txfault 200 ms time from tx fault state to tx fault bit set and intl asserted flag assert time ton_flag 200 ms time from occurrence of condition triggering fag to associated fag bit set and intl asserted. mask assert time ton_mask 100 ms time from mask bit set until associated intl assertion is inhibited mask deassert time tof_mask 100 ms time from mask bit cleared until associated intl operation resumes power set assert time ton_pdown 100 ms time from p_down bit set until module power consumption enters power level 1 power set deassert time tof_pdown 300 ms time from p_down bit cleared until the module is fully functional rx squelch assert time ton_rxsq 80 s time from loss of rx input signal until the squelched output condition is reached rx squelch deassert time tof_rxsq 80 s time from resumption of rx input signals until normal rx output condition is reached tx squelch assert time ton_txsq 400 ms time from loss of tx input signal until the squelched output condition is reached tx squelch deassert time tof_txsq 400 ms time from resumption of tx input signals until normal tx output condition is reached tx disable assert time ton_txdis 100 ms time from tx disable bit set until optical output falls below 10% of nominal tx disable deassert time tof_txdis 400 ms time from tx disable bit cleared until optical output rises above 90% of nominal rx output disable assert time ton_rxdis 100 ms time from rx output disable bit set until rx output falls below 10% of nominal rx output disable deassert time tof_rxdis 100 ms time from rx output disable bit cleared until rx output rises above 90% of nominal squelch disable assert time ton_sqdis 100 ms this applies to rx and tx squelch and is the time from bit set until squelch functionality is disabled squelch disable deassert time tof_sqdis 100 ms this applies to rx and tx squelch and is the time from bit cleared until squelch functionality is enabled
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. av02-3213en - january 25, 2013 figure 17. two-wire serial address a0xh page structure memory map the memory is structured as a single address, multiple page approach. the address is given as a0xh. the structure of the memory is shown in figure 17. the memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages of 128 bytes each. this structure permits timely access to addresses in the lower page, e.g. interrupt flags and monitors. less time critical entries, e.g. serial id information and threshold settings are available with the page select function. for a more detailed description of the qsfp+ memory map see the qsfp+ sff- 8436 specifcation or the avago technologies qsfp+ memory map document. 2-wire serial address, 1010000x (a0h)" 0 2 3 (19 bytes) 21 22 (12 bytes) 33 34 (48 bytes) 81 82 (4 bytes) 85 86 (12 bytes) 97 98 (2 bytes) 99 100 (7 bytes) 106 107 (12 bytes) 118 119 (4 bytes) 122 123 (4 bytes) 126 127 (1 bytes) 127 page 03 page 02 (optional) page 01 (optional) page 00 128 (128 bytes) 128 128 128 175 255 128 191 192 (32 bytes) (64 bytes) 129 (1 bytes) (1 bytes) 176 (48 bytes) (48 bytes) 129 223 223 224 (32 bytes) 130 (2 bytes) 224 (2 bytes) 13 1 255 225 132 (2 bytes) 226 (16 bytes) 133 241 242 (12 bytes) 253 254 (2 bytes) 254 (2 bytes) 255 255 application code entry tl reserved application code entry 1 vendor speci- c channel controls other entries channel monitor masks ast table length (tl) extended id channel threshold application code entry 0 vendor speci- c id reserved module threshold user eeprom data cc_apps base id fields reserved password change entry area (optiona l) password entry area (optional) page select byte reserved control reserved module and channel mask id and status interrupt flags module monitors channel monitors (3 bytes)

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